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| 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-STATE Outputs Product Features * PI74ALVCH162260 is designed for low voltage operation * VCC = 2.3V to 3.6V * Hysteresis on all inputs * Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25C * Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25C * Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors * Industrial operation at 40C to +85C * Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V) Product Description Pericom Semiconductor's PI74ALVCH series of logic circuits are produced in the Company's advanced 0.5 micron CMOS technology, achieving industry leading speed. The PI74ALVCH162260 is a 12-bit to 24-bit multiplexed D-type latch designed for 2.3V to 3.6 VCC operation. It is used in applications where two separate datapaths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device is also useful in memory-interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is HIGH, the latch is transparent. When the latch-enable input goes LOW, the data present at the inputs is latched and remains latched until the latch-enable input is returned HIGH. To reduce overshoot and undershoot, the B-port outputs include 26 series resistors. To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pullup resistor, the minimum value of the resistor is determined by the currentsinking capability of the driver. 1B1 Logic Block Diagram LE1B LE2B LEA1B LEA2B OE2B 2 27 30 55 56 29 OE1B 1 28 G1 A1 8 1 1 C1 23 1D OEA SEL C1 6 1D 2B1 Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. C1 1D C1 1D TO 11 OTHER CHANNELS 1 PS8127 03/17/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs Truth Tables(1) B to A (OEB = H) Inputs 1B 2B SEL LE1B LE2B OEA Output A Product Pin Description Pin Name OE SEL LE A,1B,2B A,1B,2B GND VCC Description Output Enable Input (Active LOW) Select Latch Enable Data Inputs 3-State Outputs Ground Power H L X X X X X X H L X X H H H L L L X H H L X X X X X X X H H L X L L L L L L H H L A0 H L A0 Z Product Pin Configuration OEA LE1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 LE2B SEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OE2B LEA2B 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 LEA1B OE1B X X 56-PIN V56 51 A56 A to B (OEA = H) INPUTS A H L H L H L X X X X X Note: 1. H = L= X= Z= OUTPUTS O E2B L L L L L L L H H L L 1B H L H L 1B0 1B0 1B0 Z Active Z Active 2B H L 2B0 2B0 H L 2B0 Z Z Active Active LEA1B LEA2B O E1B H H H H L L L X X X X H H L L H H L X X X X L L L L L L L H L H L High Signal Level Low Signal Level Irrelevant High Impedance 2 PS8127 03/17/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........................................................... 65C to +150C Ambient Temperature with Power Applied ........................ 40C to +85C Input Voltage Range, VIN ...................................................... 0.5V to VCC +0.5V Output Voltage Range, VOUT ............................................... 0.5V to VCC +0.5V DC Input Voltage .................................................................... 0.5V to +5.0V DC Output Current ............................................................................ 100 mA Power Dissipation .................................................................................. 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parame te rs VCC VIH VIL VIN VOUT IOH De s cription Supply Voltage Input HIGH Voltage Te s t Conditions M in. 2.3 Typ. M ax. 3.6 Units VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V 2.0 1.7 0.8 0.7 0 0 VCC VCC - 12 - 12 - 24 12 12 24 -6 -8 - 12 6 8 12 - 40 85 C mA V Input LOW Voltage Input Voltage Output Voltage High- level output current (A Port) VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 2.3V VCC = 2.7V VCCC = 3.0V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOL Low- level output current (A Port) IOH High- level output current (B Port) IOL TA Low- level output current (B Port) Operating free- air temperature Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 3 PS8127 03/17/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs DC Electrical Characteristics (Over the Operating Range, TA = -40C to +85C, VCC = 3.3V 10%) Parame te rs Te s t Conditions IOH = - 100mA IOH = - 6mA VOH (A PORT) IOH = - 12mA IOH = - 24mA IOH = - 100mA IOH = - 4mA VOH (B PORT) IOH = - 6mA IOH = - 8mA IOH = - 12mA IOL = 100mA IOL = 6mA VOL (A PORT) IOL = 12mA IOL = 24mA IOL = - 100mA IOL = 4mA VOL (B PORT) IOL = 6mA IOL = 8mA IOL = 12mA II VI = VCC or GND VIN = 0.7V VIN = 1.7V II (Hold) VIN = 0.8V VIN = 2.0V IOZ(3) ICC DICC VIN = 0 to 3.6V VO = VCC or GND VI = VCC or GND One input at VCC = 0.6V. Other inputs at VCC or GND VIL = 0.7V VIL = 0.7V VIL = 0.8V VIL = 0.8V VIL = 0.8V VIL = 0.7V VIL = 0.7V VIL = 0.8V VIL = 0.8V VIH = 1.7V VIH = 1.7V VIH = 2.0V VIH = 2.0V VIH = 2.0V VIH = 1.7V VIH = 1.7V VIH = 2.0V VIH = 2.0V VIH = 2.0V VCC(1) Min. to Max. 2.3 V 2.3 V 2.7 V 3.0 V 3.0 V Min. to Max. 2.3 V 2.3 V 3.0 V 2.7 V 3.0 V Min. to Max. 2.3V 2.3V 2.7V 3.0V Min. to Max. 2.3V 2.3V 3.0V 2.7V 3.0V 3.6V 2.3V 3.0V 3.6V 3.6V 3.6V 3.3V to 3.6V 3.3V 3.3V 3.5 4.5 45 - 45 75 - 75 500 10 40 750 pF mA M in. VCC - 0.2 2.0 1.7 2.2 2.4 2.0 VCC - 0.2 1.9 1.7 2.4 2.0 2.0 0.2 0.4 0.7 0.4 0.55 0.2 0.4 0.55 0.55 0.6 0.8 5 V Typ.(2) M ax. Units CI Control Inputs VIN = VCC or GND CIO A or B ports VO = VCC or GND Notes: 1. For Max. or Min. conditions use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25C ambient and maximum loading. 3. This is the bus-hold maximum dynamic current required to swtich the input from one state to another. 4 PS8127 03/17/98 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH162260 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs VCC = 2.7V M in. M ax. 150 3.3 1.1 1.9 3.3 1.1 1.5 0 10 ns/V ns VCC = 3.3V 0.3V M in. M ax. 150 Timing Requirements over Operating Range Parame te rs fCLOCK tW tSU tH Dt/D(1) De s cription Clock Frequency Pulse duration, LE1B, LE2B, LEA1B, or LEA2B High Setup time, data before LE1B, LE2B, LEA1B, or LEA2B Hold time, data after LE1B, LE2B, LEA1B or LEA2B Input Transition Rise or Fall 3.3 1.4 1.6 VCC = 2.5V 0.2V M in. M ax. 150 Units MHz Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. Switching Characteristics over Operating Range(1) Parame te rs fMAX A B tPD LE LE SEL tEN tDIS OE OE OE OE B A A B A A B A B From To (INPUT) (OUTPUT) VCC = 2.5V 0.2V M in.(2) 150 1.2 1.2 1.0 1.0 1.2 1.0 1.0 1.7 1.7 6.5 6.0 6.2 6.7 7.5 7.2 7.7 5.9 6.4 M ax. VCC = 2.7V M in.(2) 150 5.8 5.1 5.2 5.9 6.6 6.4 7.1 5.0 5.5 M ax. VCC = 3.3V 0.3V M in.(2) 150 1.2 1.2 1.0 1.0 1.1 1.0 1.0 1.3 1.3 4.9 4.3 4.4 5.0 5.6 5.4 6.0 4.6 5.1 ns M ax.(2) Units MHz Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. Operating Characteristics, TA = 25C Parame te r CPD Power Dissipation Capacitance O utputs Enabled O utputs Disabled Te s t Conditions CL = 50pF, f = 10 MHz VCC = 2.5V 0.2V 62 29 VCC = 3.3V 0.3V 46 24 Typical Units pF Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 5 PS8127 03/17/98 |
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